Sample-and-hold circuit with enhanced noise limit

ABSTRACT

A sample-and-hold circuit is presented that is current driven at the input and current sensed at the output, using two capacitors—one at the input to the ground and second past a pair of complementary CMOS switches at the output to the ground. These capacitors in connection with an input current drive form a highpass noise transfer function that substantially reduces the 1/f noise of the switches and then rolls the transfer function off, further reducing the noise. The overall noise level is significantly lower as compared to a conventional voltage-driven and voltage-sensed sample-and-hold circuit that has a lowpass transfer function which, after integration, demonstrates a noise limit of kT/C. Depending on the circuit parameters the present sample-and-hold circuit shows an integrated noise improvement of between 5 and 10 dB over kT/C limit.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention generally relates to sample-and-hold circuits,such as those utilized at the front of analog to digital converters and,more particularly, to a sample-and-hold circuit that is current drivenat the input and current sensed at the output.

2. Description of the Related Art

Sample-and-hold (S/H) circuits are used to provide discrete signalvalues, necessary at the input of an analog to digital converter (ADC).One of the most important parameters of a S/H circuit is the amount ofthermal noise it generates. This value often determines the necessaryresolution, or necessary number of bits required for an ADC.Conventionally, the majority of S/H circuits are voltage-driven at theinput and voltage-sensed at the output. For such a circuit its frequencyresponse is a one-pole low-pass filter with pole value at f=1/(2π·R_(ON)·C), where f is the pole frequency, R_(ON) is the switch on-resistance,and C is the value of a sampling capacitor. If this noise is integratedover the S/H bandwidth, its value is kT/C, where k is the Boltzmannconstant and T is the Kelvin temperature.

In recent years this value has been an undisputed limit of S/H thermalnoise performance. However, a need has developed to lower the amount ofS/H thermal noise in order to limit the number of required ADC bits,which may result in a smaller ADC footprint and its reduced powerconsumption.

It would be advantageous if a S/H circuit existed having a lowpasssignal transfer function and a highpass noise transfer function with thepotential of lowering thermal noise below the kT/C value.

SUMMARY OF THE INVENTION

A sample and hold (S/H) circuit is provided herein that is currentdriven at the input and current sensed at the output. A first capacitor,to ground, is connected at the input to a pair of complementarymetal-oxide-semiconductor (CMOS) switches, and a second (optional)capacitor, to ground, is connected to CMOS switch output. Optionally, asingle field effect transistor (FET) may be used as the switch. Thefirst capacitor, in cooperation with an input current drive, forms ahighpass noise transfer function that substantially reduces the 1/f(flicker) noise of the switch(es). The second capacitor helps improvethe noise transfer rolls-off further, reducing the overall noise. Theoverall noise level is significantly lower than a conventionalvoltage-driven and voltage-sensed sample-and-hold circuit that has alowpass transfer function and that after integration demonstrates anoise limit of kT/C, where k is the Boltzmann constant, T is theabsolute temperature in Kelvin, and C is a value of a samplingcapacitor. Depending on the circuit parameters, the sample-and-holdcircuit presented herein shows an integrated noise improvement ofbetween 5 and 10 decibels (dB) below the kT/C limit.

Accordingly, a sample-and-hold circuit with an enhanced noise limit isprovided. The S/H circuit uses at least a first field effect transistor(FET) having a first source drain (S/D) to accept an analog input signalcurrent (I_(S)), a second S/D, and a gate to accept a binary level firstdigital control signal. A source resistance (Rs), representedschematically as source resistor (R_(S)), has a first terminal connectedto the first S/D of the first FET and a second terminal connected toground. A first capacitor (C₁) has a first terminal connected to thefirst S/D of the first FET and a second terminal connected to ground. Asa result, the second S/D of the first FET presents a current-sensedanalog output signal (I_(O)) in response to the first digital controlsignal enabling the first FET at a first time. In one aspect, a secondcapacitor has a first terminal connected to the second S/D of the firstFET and a second terminal connected to the reference voltage. Asmentioned above, in another aspect a complementary second FET has asecond S/D connected to the first S/D of the first FET, a first S/Dconnected to the second S/D of the first FET, and a gate to accept abinary level second digital control signal, complementary to the firstdigital control signal. The second digital control signal enables thesecond FET at the first time.

Additional details of the above-described current-mode S/H circuit arepresented below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic diagrams of a current-driven,current-sensed sample- and hold-circuit using, respectively, a singleFET and complementary switches.

FIG. 2 is a schematic diagram of the S/H current-mode circuit with idealcomponents supporting the derivation of the signal transfer function.

FIG. 3 is a schematic diagram of the S/H current-mode circuit with idealcomponents supporting the derivation of the noise transfer function.

FIG. 4 is a schematic diagram of a voltage-mode sample and holdtest-bench circuit.

FIG. 5 is a schematic diagram of the voltage-sensed circuit driven by asignal current source.

FIG. 6 is a schematic diagram of the voltage-sensed, current-drivencircuit supporting the derivation of a voltage transfer function.

FIG. 7 is a schematic diagram of the voltage-sensed, current-drivencircuit supporting the derivation of a noise transfer function.

FIG. 8 is a graph contrasting two noise transfer functions.

FIG. 9 is a first graph showing two principles of 1/f noise handling.

FIG. 10 is a second graph showing two principles of 1/f noise handling.

FIG. 11 is the schematic diagram of FIG. 2 featuring the addition of asecond capacitor for steeper noise roll-off.

FIG. 12 is a graph depicting two noise transfer functions for thecurrent-sensed, current-driven S/H circuit.

DETAILED DESCRIPTION

FIGS. 1A and 1B are schematic diagrams of a current-driven,current-sensed sample and hold circuit using, respectively, a single FETand complementary switches. The sample-and-hold (S/H) circuit 10 uses aswitch enabled with a single field effect transistor (FET) 11, as shownin FIG. 1A, or enabled with a pair of complementary switches 12 (e.g.,FETs such as complementary metal-oxide-semiconductor CMOS transistors),as shown in FIG. 1B. The switch or switches are connected to the inputcapacitor C₁ 14 through their input source/drain (S/D) terminals. Thecomplementary switch 12 does not change the noise performance, but itsubstantially improves the linearity. Switch 11 or 12 is excited by aninput analog signal current source 16 with a source resistance (Rs),represented as source resistor R_(S) 18, between the FET (FIG. 1A) orFETS (FIG. 1B) and ground.

Furthermore, the gate of switch 11 (FIG. 1A) is pulsed with binary valuedigital voltage source V_(p) 20, and the gates of switch 12 (FIG. 1B)are pulsed by two complementary digital voltage sources V_(P) and V_(P)_(_) _(BAR) denoted, respectively, by reference designators 20 and 22.The digital voltage source enables the switch(es) to selectively passcurrent or prevent current flow. The output current I_(O) on line 24 ison the other side of the switch 11 (FIG. 1A) or switches 12 (FIG. 1B),away from the C₁ capacitor 14.

FIG. 2 is a schematic diagram of the S/H current-mode circuit with idealcomponents supporting the derivation of the signal transfer function.The model 30 consists of 4 elements only. The transconductance of theFET in FIG. 1A or the complementary switches in FIG. 1B is denoted byg_(m) and is identified by reference designator 32. Capacitance C₁ isidentified by reference designator 34, and a signal source I_(S) with asignal source resistance (Rs), represented schematically as input orsource resistor R_(S), are respectively identified by the referencedesignators 36 and 38. Finally, the output current I_(O) is identifiedwith the reference designator 40 and it is taken on the opposite side ofthe transistor(s) from capacitor 34.

The current signal transfer function of the current-mode S/H of FIGS. 1Aand 1B is I_(O)/I_(S)=g_(m)/(g_(m)+sC₁), which is a first-order lowpassfunction.

$\begin{matrix}{I_{S} = {I_{Rs} + I_{C\; 1} + I_{gm}}} \\{= {V_{S}*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)}} \\{= {\left( {I_{O}/g_{m}} \right)*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)}}\end{matrix}$ I_(O)/I_(S) = g_(m)/(1/R_(S) + g_(m) + sC₁)If  1/R_(S) ⪡ g_(m) =  > I_(Rs) ≈ 0 I_(O)/I_(S) = g_(m)/(g_(m) + sC₁)

where C₁ is the capacitance value of C₁; and,

where Rs is the resistance value of Rs.

FIG. 3 is a schematic diagram of the S/H current-mode circuit with idealcomponents supporting the derivation of the noise transfer function. Themodel 50 comprises the transconductance of the FET (FIG. 1A) or thecomplementary switches (FIG. 1B), denoted by g_(m) and identified by thereference designator 60. A switch noise current source is denoted byI_(n),g_(m) and identified by reference designator 62. Capacitance C₁ isidentified by reference designator 52, and the signal source I_(S) withthe source resistance (Rs), as represented schematically by sourceresistance R_(S), are respectively identified by the referencedesignators 54 and 56. The voltage V_(S) at the current input of thetransistors is identified with reference designators 58. Finally, theoutput current I_(O) is identified with reference designator 64 and itis taken on the opposite (current-sensed) side of switch(es) fromcapacitor 52.

The current noise transfer function of the S/H circuit isI_(O)/I_(n,gm)=sg_(m)C₁/(g_(m)+sC₁), which is a first-order highpassfunction. The combined transfer function that uses noise transfer incombination with signal transfer is calculated to be(I_(O)/I_(n,gm))*(I_(O)/I_(S))=sC₁/(g_(m)+sC₁)*g_(m)/(g_(m)+sC₁)=sg_(m)C₁/(g_(m)+sC₁)².This function has a zero at dc—(zero Hertz) and a double pole atg_(m)/C₁. As it is shown in FIG. 8, one pole compensates for zero andthe transfer is flat after pole frequency g_(m)/C₁. However, second polegives the transfer a desired drop-off after the double-pole frequencyg_(m)/C₁.

$\begin{matrix}{I_{O} = {I_{n,{Rs}} + I_{Rs} + I_{C\; 1} - I_{n,{gm}} + I_{gm}}} \\{= {I_{n,{Rs}} - I_{n,{gm}} + {V_{S}*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)}}}\end{matrix}$ If  1/R_(S) ⪡ g_(m) =  > I_(n, Rs) + I_(Rs) ≈ 0Also, at  high  frequency  I_(O) ≈ I_(C 1)and  I_(n, gm) ≈ I_(gm) + I_(C 1) $\begin{matrix}{{I_{O}/I_{n}} = {I_{C\; 1}/\left( {I_{gm} + I_{C\; 1}} \right)}} \\{= {V_{S}*{{sC}_{1}/\left( {g_{m} + {sC}_{1}} \right)}*V_{S}}} \\{= {{sC}_{1}/\left( {g_{m} + {sC}_{1}} \right)}}\end{matrix}$${Combined}\mspace{14mu}{noise}\mspace{14mu}{transfer}\mspace{14mu}{{function}:\begin{matrix}{{\left( {I_{O}/I_{n,{gm}}} \right)*\left( {I_{O}/I_{S}} \right)} = {{{sC}_{1}/\left( {g_{m} + {sC}_{1}} \right)}*{g_{m}/\left( {g_{m} + {sC}_{1}} \right)}}} \\{= {{sg}_{m}{{sC}_{1}/\left( {g_{m} + {sC}_{1}} \right)^{2}}}}\end{matrix}}$

FIG. 4 is a schematic diagram of a voltage-mode sample and holdtest-bench circuit. The voltage-mode S/H circuit 70 includes a singleswitch M1, as shown here in the interest of simplicity, but mayalternatively be a pair of complementary switches such as shown in FIG.1B. M1 is identified by reference designator 76 and is connected to anoutput capacitor C₁ 74. Switch 76 is excited by an input analog signalvoltage source 82 with a source resistance (Rs), representedschematically by source resistor R_(S) 80. Additionally, the switch 76is pulsed from a digital voltage source 84. Two voltages are present inthis circuit: the input voltage V_(S) 82 and the output voltage V_(O)72. The derivation of transfer functions is easier if the voltage signalsource 82 is replaced a current source, as described in the explanationof FIG. 5 below.

FIG. 5 is a schematic diagram of the voltage-sensed circuit driven by asignal current source. The voltage-mode S/H circuit 90 of FIG. 5 isderived from the circuit of FIG. 4. It includes a single switch M1 96that is connected to an output capacitor C₁ 94. Switch 96 is excited byan input analog signal current source 100 with a source resistance (Rs),represented schematically by source resistor R_(S) 102. Additionally,the switch 96 is pulsed from a digital voltage source 104. Two voltagesare present in this circuit: the input voltage V_(S) 98 and the outputvoltage V_(O) 92.

FIG. 6 is a schematic diagram of the voltage-sensed, current-drivencircuit supporting the derivation of a voltage transfer function. Themodel 110 comprises 4 elements only. The transconductance of the switch96 is denoted by g_(m) and identified with reference designator 116. Themodel 110 also comprises capacitance C₁ 114, signal source I_(S) 120,and source resistance (Rs), represented schematically by source resistorR_(S) 122. Finally, the output voltage V_(O) 112 and it is taken on theopposite side of the switch from capacitor 114. Additionally, the inputvoltage V_(S) is identified with reference designator 118.

The voltage signal transfer function of the voltage-mode S/H isV_(O)/V_(S)=g_(m)/(g_(m)+sC₁), which is a first-order lowpass function.

I_(S) + I_(Rs) = I_(gm) I_(S) + V_(S)/R_(S) = (V_(S) − V_(O)) * g_(m)I_(S) = V_(S) * (1/R_(S) + g_(m)) − V_(O) * g_(m)If  1/R_(S) ⪡ g_(m) =  > I_(Rs) ≈ 0 I_(C 1) = V_(O) * sC₁ = I_(S)I_(S) = V_(S) * g_(m) − (I_(S)/sC₁) * g_(m)I_(S) + (I_(S)/sC₁) * g_(m) = V_(S) * g_(m)I_(S) * (1 + g_(m)/sC₁) = V_(S) * g_(m)V_(O) * sC₁ * (1 + g_(m)/sC₁) = V_(S) * g_(m)V_(O)/V_(S) = g_(m)/(g_(m) + sC₁)

FIG. 7 is a schematic diagram of the voltage-sensed, current-drivencircuit supporting the derivation of a noise transfer function. Themodel 130 comprises switch transconductance 136, denoted by g_(m), aswitch noise current source 144 denoted by I_(n),g_(m), capacitance C₁134, a signal current source I_(S) 140, and source resistance (Rs),represented schematically by source resistor R_(S) 142. The voltageV_(S) at the input to the switch is identified with reference designator138. Finally, the output voltage V_(O) 132 is taken from the same sideof a switch as capacitor 134.

The voltage noise transfer function of the voltage-mode S/H isV_(O)/V_(n,gm)=g_(m)/(g_(m)+sC₁), which is a first-order lowpassfunction.

I_(n, Rs) + I_(Rs) = I_(n, gm) + I_(gm)If  1/R_(S) ⪡ g_(m) =  > I_(n, Rs) + I_(Rs) ≈ 0I_(C 1) = I_(n, gm) − I_(gm) I_(C 1) = V_(O) * sC₁V_(O) * sC₁ = I_(n, gm) − V_(O) * g_(m)I_(n, gm) = V_(O) * (g_(m) + sC₁) I_(n, gm) = V_(n, gm) * g_(m)V_(n, gm) * g_(m) = V_(O) * (g_(m) + sC₁)V_(O)/V_(n, gm) = g_(m)/(g_(m) + sC₁)

FIG. 8 is a graph contrasting two noise transfer functions. The lowpassgraph (sections 152 and 158) is associated with a voltage-mode circuit.It is flat until the pole frequency of f_(P). Then it rolls-of due toits pole. A highpass graph is associated with a current-mode circuit.Its response 154 increases until the pole frequency of f_(P). Then itflattens due to its pole (section 156). Practically, however, two polesare present at f_(P). Therefore, the current-mode noise transfer 160rolls-off similarly to the voltage-mode circuit (section 158).

For a voltage-driven circuit both transfer functions for signal andnoise are the same:V _(O) /V _(S) =g _(m)/(g _(m) +sC ₁)V _(O) /V _(n,gm) =g _(m)/(g _(m)+sC ₁)

In order to calculate the total thermal noise contribution certainassumptions need to be made:

1) We calculate only the ½ of the total bandwidth, exactly to the poleposition and not beyond to be comparable with the current-driven circuitthat takes the same bandwidth.

2. We use an approximation that 1/R_(S)<<g_(m), which results in muchsimpler transfer function. Hence:(V _(O) /V _(n,gm))² |=|H(jω)² |=|g _(m) ²/(g _(m) ²+ω² C ²)|=|1/(1+ω² C² /g _(m) ²)|

In order to calculate the bandwidth, we need to integrate |H(jω)²| from0 to 1. 1 corresponds to ω_(P)=g_(m)/C, which is the pole frequency.

∫₀¹d ω/(1 + ω²C²/g_(m)²) = g_(m)/C∫₀¹dx/(1 + x²) = (g_(m)/C) * arctan |₀¹ = (g_(m)/C) * (π/4 − 0) = (g_(m)/C) * (π/4)$\mspace{20mu}{{Hence}:\begin{matrix}{{V^{2}(f)}_{noise} = {{4{kT}*\left( {1/g_{m}} \right)*{{BW}(\omega)}*\left( {{1/2}\pi} \right)} = {4{kT}*\left( {1/g_{m}} \right)*\left( {g_{m}/C} \right)*}}} \\{\left( {\pi/4} \right)*\left( {{1/2}\pi} \right)} \\{= {{4{kT}*\left( {1/C} \right)*\left( {1/8} \right)} = {{{kT}/2}{C.}}}}\end{matrix}}$

This can be further converted to: kT/2C=(kTω)/(2g_(m)).

For the current-driven circuits of FIG. 1A or 1B, the transfer functionfor signal is LP (lowpass) and the transfer function for noise is HP(highpass):I _(O) /I _(S) =g _(m)/(g _(m) +sC ₁)I _(O) /I _(n) =sg _(m) C ₁/(g _(m)+sC ₁)

In order to calculate the total thermal noise contribution certainassumptions need to be made:

3) We calculate only the ½ of the total bandwidth, exactly to the poleposition and not beyond to be comparable with the voltage-sensed circuitthat takes the same bandwidth.

4) We use the approximation that 1/R_(S)<<g_(m), which results in muchsimpler transfer function.

5) The combined transfer function for noise has the equation:sg _(m) C/(g _(m) +sC)².

Hence:

$\begin{matrix}{{{H\left( {j\;\omega} \right)}^{2}} = {{{\left( {\omega\; C} \right)^{2}{g_{m}^{2}/\left( {g_{m}^{2} + {\omega^{2}C^{2}}} \right)^{2}}}} = {\left\lbrack {\left( {\omega\; C} \right)^{2}\left( {g_{m}^{2}/g_{m}} \right)^{4}} \right\rbrack/\left\lbrack \left( {1 +} \right. \right.}}} \\\left. \left. {\omega^{2}{C^{2}/g_{m}^{2}}} \right)^{2} \right\rbrack \\{= {\left( {C^{2}/g_{m}^{2}} \right)*{(\omega)^{2}/\left\lbrack \left( {1 + {\omega^{2}{C^{2}/g_{m}^{2}}}} \right)^{2} \right\rbrack}}}\end{matrix}$

In order to calculate the bandwidth, we need to integrate |H(jω)²| from0 to 1. 1 corresponds to ω_(P)=g_(m)/C, which is the pole frequency.

$\begin{matrix}{{\left( {C^{2}/g_{m}^{2}} \right)*{\int_{0}^{1}{\omega^{2}d\;{\omega/\left\lbrack \left( {1 + {\omega^{2}{C^{2}/g_{m}^{2}}}} \right)^{2} \right\rbrack}}}} = {{g_{m}/{C\left( {C^{2}/g_{m}^{2}} \right)}}\left( {g_{m}^{2}/} \right.}} \\{\left. \left. C^{2} \right) \right){\int_{0}^{1}{x^{2}{{dx}/\left( {1 + x^{2}} \right)^{2}}}}} \\{= {\left( {g_{m}/C} \right)*\left\{ {1/{2\left\lbrack {{- x}/} \right.}} \right.}} \\{\left. \left. {\left( {1 + x^{2}} \right) + {\arctan(x)}} \right\rbrack \right\}|_{0}^{1}} \\{= {\left( {g_{m}/C} \right)*\left\lbrack {{1/2}\left( \left( {{- 1}/} \right. \right.} \right.}} \\\left. {\left( {1 + 1} \right) + {\pi/4} - 0} \right) \\{= {\left( {g_{m}/C} \right)*{\left( {{\pi/8} - {1/4}} \right).}}}\end{matrix}$ ${Hence},\begin{matrix}{{I^{2}(f)}_{noise} = {4{kT}*g_{m}*{{BW}(\omega)}*\left( {{1/2}\pi} \right)}} \\{= {4{kT}*g_{m}*\left( {g_{m}/C} \right)*\left( {{\pi/8} - {1/4}} \right)*\left( {\pi/2} \right)*\left( {{1/2}\pi} \right)}} \\{= {0.1427*{{kT}/C}*{\omega^{2}.}}}\end{matrix}$

This can be further converted to: 0.1427*kT/C*ω²=0.1427*kT*ω*g_(m).

In order to compare the noise performance for both circuits, the totalthermal noise contributions are divided:Voltage-driven circuit: V ²(f)_(noise)=(kTω)/(2g _(m)).This can be converted into current: I ²(f)_(noise) =kTω*g _(m)/2.Current-driven circuit: I ²(f)_(noise)=0.1427*kT*ω*g _(m).

Hence, the improvement can be calculated as a ratio:(kTω*g _(m)/2)/0.1427*kT*ω*g _(m)=0.5/0.1427=3.5,or in dBs: 10 log₁₀(3.5)=5.445 dB≈5.4 dB.

In some aspects the total noise improvement may reach 10 dB or more.This can be explained as follows. Practical modern MOS devices have asignificant 1/f noise contribution. In current deep-submicron CMOStechnologies the 1/f noise corner can be anywhere from 10 MHz to 100MHz.

FIG. 9 is a first graph showing two principles of 1/f noise handling.The solid line 162 is associated with to a voltage-mode circuit thatintegrates 1/f (flicker) noise until the sampling frequency of f_(S).The result of this integration is b²/3, where b²=H(1)². The dashed line164 is associated with a current-mode circuit. Because of its highpassnoise transfer it integrates a flat spectrum until f_(S). The result ofthis integration is b²/f_(S). The ratio of these two integrations givesa 1/f noise improvement of current-mode over voltage-mode circuitry,which is calculated to be f_(S)/3.

Referring to FIGS. 8 and 9, it can be seen that with a voltage-drivencircuit provides no help for the suppression of 1/f noise. This is aresult of lowpass (LP) noise characteristics that pass all 1/f noise tothe output. This can be represented graphically (see the FIGS. 8 and 9),or numerically as follows.|I ₁(f)² |=a ²/(f)²/[1+(2π)² f ² C ² ₁ /g ² _(m)]≈a ²/(f)² for f<g_(m)/(2πC ₁)

For an ideal current-driven circuit with zero at the origin the 1/fnoise is flattened, meaning there is no high noise value at f=0, andthen a linear drop-off until the 1/f corner.|I ₂(f)² |=a ² /BW ² for f<g _(m)/(2πC ₁)

The spectrum starts from zero Hertz and it is flat. Hence, afterintegration the residuum 1/f noise looks like a thermal noise.

Calculating the integrals in both cases, BW=10 MHz and BW<g_(m)/(2πC₁).

Voltage Case:S ² ₁(f)=a ²*∫¹ _(BW) df/f ² =a ²/3*/f ³|¹ _(BW) =a ²/3*[1−1/(BW)³]≈a²/3, wherea ²=1/f noise power value for f=1 Hz, or |I ₁(1)² |=a ²

Current Case:

$\begin{matrix}{{S_{2}^{2}(f)} = {a^{2}*{\int_{1}^{BW}{\left( {{df}/f^{2}} \right)*\left( {C^{2}/g_{m}^{2}} \right)*{\left( {2\pi\; f} \right)^{2}/\left\lbrack \left( {1 + {\left( {2\pi\; f} \right)^{2}{C^{2}/}}} \right. \right.}}}}} \\\left. \left. g_{m}^{2} \right)^{2} \right\rbrack \\{\approx {a^{2}{\int_{1}^{BW}{{C^{2}/{g_{m}^{2}\left( {2\pi} \right)}^{2}}{df}}}}} \\{= {{{\left( {a^{2}/{BW}^{2}} \right)*f}|_{1}^{BW}} = {\left( {a^{2}/{BW}^{2}} \right)*\left\lbrack {{BW} - 1} \right\rbrack}}} \\{{\approx {\left( {a^{2}/{BW}^{2}} \right)*{BW}}} = {a^{2}/{BW}}}\end{matrix}$ S₁²(f)/S₂²(f) = (1/3) * BW = 3.33 * 10⁶, or10log₁₀(3.33 * 10⁶) ≈ 65.2  dB

Theoretically, the total 1/f noise improvement is 65 dB. However, thisresult is not always practical.

FIG. 10 is a second graph showing two principles of 1/f noise handling.The solid line 172 is associated with a voltage-mode circuit, whichintegrates 1/f noise until the sampling frequency of f_(S). Between acorner frequency f_(P) and sampling frequency f_(S), the graph portionis identified by the numeral 176 and is still of 1/f type. A flatspectrum identified by the numeral 174 is associated with a current-modecircuit. Due to the highpass (HP) characteristics of the current-modecircuit, from a corner frequency f_(P) to a sampling frequency f_(S),the dashed-line graph portion identified by reference designator 174 isflat. That is, to compare the two circuits an intermediate frequencypoint f_(P) is taken into account. At this frequency the current-modecircuit regains its highpass noise transfer function. As a result,between f_(P) and f_(S), the voltage-mode circuit integration noise isc²/3, where c²=H(f_(P))², and a current-mode circuit integration noise174 is c²/(f_(S)−f_(P)). The ratio of these two integrals gives the 1/fnoise improvement of current-mode over voltage-mode circuitry. In thiscase, it is calculated to be (f_(P)−f_(S))/3.

For simplicity, an assumption that 1/R_(S)<<g_(m) is used. If thisassumption is not used the current-mode noise transfer is not highpassat dc (zero Hertz), but it is flat and then becomes highpass from acertain frequency. For example, if this corner is at 1 megahertz (MHz),then for first 1 MHz the current-driven circuit behaves like avoltage-driven circuit. But at 1 MHz the HP behavior starts and for next1 decade until 10 MHz, the 1/f noise remains flat. The perceivedadvantage is around 4.8 dB.S ² ₃(f)=(b ²/3)[1−1/(10−1)³]=(b ²/3)[1− 1/9³]≈b ²/3 for voltage-mode circuit.S ² ₄(f)=b ²/(10−1)=b ²/9 for current-mode circuit.S ² ₃(f)/S ² ₄(f)=(b ²/3)/(b ²/9)=3, or 10 log₁₀(3)≈4.8 dB, see FIG. 10.

So, the total improvement should be around 5.4 dB for a flat thermalnoise and 4.8 dB for i/f noise, totaling 10.2 dB.

FIG. 11 is the schematic diagram of FIG. 2 featuring the addition of asecond capacitor for steeper noise roll-off. The model 180 includesoutput current I_(O) 182, output capacitor C₂ 184, the output voltageV_(O) on line 186, switch transconductance 196, input resistance (Rs),represented schematically as resistor R_(S) 194, input current sourceI_(S) 192, source voltage V_(S) 190, output resistance (Ro), representedschematically as resistor R_(O) 198, and input capacitor C₁ 188.

$\begin{matrix}{{V_{O} = {{- R_{O}}*I_{O}}},{I_{S} = {{I_{Rs} + I_{C\; 1} + I_{gm}} = {{V_{S}*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)} -}}}} \\{{V_{O}*g_{m}} - I_{O}} \\{= {{I_{C\; 2} + I_{gm}} = {{V_{O}*\left( {{sC}_{2} + g_{m}} \right)} - {V_{S}*g_{m}}}}} \\{= {{R_{O}*I_{O}*\left( {{sC}_{2} + g_{m}} \right)} - {V_{S}*g_{m}}}}\end{matrix}$ $\begin{matrix}{I_{S} = {{{V_{S}*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)} + {R_{O}*I_{O}*g_{m}}} = {> V_{S}}}} \\{= {I_{O}*{\left\lbrack {{R_{O}\left( {{sC}_{2} + g_{m}} \right)} + 1} \right\rbrack/g_{m}}}}\end{matrix}$

where Ro represents the resistance value of Ro; and,

where C₂ represents the capacitance value of C₂.

$\begin{matrix}{I_{S} = {{\left\{ {I_{O}*{\left\lbrack {{R_{O}\left( {{sC}_{2} + g_{m}} \right)} + 1} \right\rbrack/g_{m}}} \right\}*\left( {{1/R_{S}} + g_{m} + {sC}_{1}} \right)} + {R_{O}*I_{O}*g_{m}}}} \\{= {{\left( {I_{O}/g_{m}} \right)*\left\lbrack {{R_{O}\left( {{sC}_{2} + g_{m}} \right)} + 1} \right\rbrack*\left( {{1/R_{S}} + {sC}_{1}} \right)} + {\left( {I_{O}/g_{m}} \right)*}}} \\{{\left\lbrack {{R_{O}\left( {{sC}_{2} + g_{m}} \right)} + 1} \right\rbrack*g_{m}} + {R_{O}*I_{O}*g_{m}}} \\{= {{{\left( {I_{O}/g_{m}} \right)*\left\lbrack {{R_{O}\left( {{sC}_{2} + g_{m}} \right)} + 1} \right\rbrack*\left( {{1/R_{S}} + {sC}_{1}} \right)} + {I_{O}*\left( {{{sR}_{O}C_{2}} + 1} \right)}} =}} \\{\left( {I_{O}/g_{m}} \right)*\left\lbrack {{{sC}_{2}{R_{O}/R_{S}}} + {g_{m}{R_{O}/R_{S}}} + {1/R_{S}} + {s^{2}R_{O}C_{1}C_{2}} +} \right.} \\{\left. {{{sg}_{m}R_{O}C_{1}} + {sC}_{1}} \right\rbrack + {{I_{O}/g_{m}}*\left( {{{sg}_{m}R_{O}C_{2}} + g_{m}} \right)}}\end{matrix}$ $\begin{matrix}{{I_{O}/I_{S}} = {g_{m}/\left\lbrack \left( {{{sC}_{2}{R_{O}/R_{S}}} + {g_{m}{R_{O}/R_{S}}} + {1/R_{S}} + {s^{2}R_{O}C_{1}C_{2}} +} \right. \right.}} \\\left. {\left. {{{sg}_{m}R_{O}C_{1}} + {sC}_{1}} \right) + \left( {{{sR}_{O}C_{2}} + 1} \right)} \right\rbrack \\{= {g_{m}/\left\lbrack {{s^{2}R_{O}C_{1}C_{2}} + {s\left( {{C_{2}{R_{O}/R_{S}}} + {g_{m}R_{O}C_{1}} + C_{1} + {g_{m}R_{O}C_{2}}} \right)} +} \right.}} \\\left. {{g_{m}{R_{O}/R_{S}}} + {1/R_{S}} + g_{m}} \right\rbrack\end{matrix}$  Since  R_(O)  is  high, then  g_(m) * R_(O) ⪢ 1.  In  some  aspects  $\mspace{20mu}{{{g_{m}*R_{O}} > {10\mspace{14mu}{hence}}},\begin{matrix}{{I_{O}/I_{S}} \approx {g_{m}/\left\lbrack {{s^{2}R_{O}C_{1}C_{2}} + {{sg}_{m}{R_{O}\left( {C_{1} + C_{2}} \right)}} + {g_{m}{R_{O}/R_{S}}}} \right\rbrack}} \\{= {\left( {{g_{m}/R_{O}}C_{1}C_{2}} \right)/\left\lbrack {s^{2} + {{{{sg}_{m}\left( {C_{1} + C_{2}} \right)}/C_{1}}C_{2}} + {{g_{m}/R_{S}}C_{1}C_{2}}} \right\rbrack}}\end{matrix}}$$\mspace{20mu}{{\omega_{O}^{2} = {{g_{m}/R_{S}}C_{1}C_{2}}},\mspace{20mu}\begin{matrix}{{\omega_{O}/Q} = {{{g_{m}\left( {C_{1} + C_{2}} \right)}/C_{1}}C_{2}{\left. \sqrt{}\left( {{g_{m}/R_{S}}C_{1}C_{2}} \right) \right./O}}} \\{= {{{g_{m}\left( {C_{1} + C_{2}} \right)}/C_{1}}C_{2}}}\end{matrix}}$$Q = {{{{\left. \sqrt{}\left( {{g_{m}/R_{S}}C_{1}C_{2}} \right) \right./{g_{m}\left( {C_{1} + C_{2}} \right)}}/C_{1}}C_{2}} = {\left. \sqrt{}\left( {C_{1}{C_{2}/g_{m}}R_{S}} \right) \right./\left( {C_{1} + C_{2}} \right)}}$Q = C/2C = 0.5, g_(m) ≈ R_(S), ω_(O) = 1m/10p = 1 * 10⁸ =  > f_(O) = 15.9  MHz.

FIG. 12 is a graph depicting two noise transfer functions for thecurrent-sensed, current-driven S/H circuit. The highpass portion 202increases until the pole frequency of f_(P). Then it rolls-of due to itspoles. Two cases are possible. One is when only one input capacitor C₁is present, with one real pole 204. In the second case two capacitors,the input C₁ and the output C₂, are present, with two complex poles 206.Thus, with the second capacitor the HP transfer has not one-real pole,but two complex poles giving it a preferred steeper −40 dB per decaderoll-off, instead of 20 dB per decade a roll-off.

It should be noted that for g_(m)≈R_(S) and for C₁=C₂ the Q=0.5 is low.The system is critically dumped. It demonstrates no overshoot and fastresponse. However, even with such a low Q the roll-off is 40 dB perdecade and not 20 dB per decade as in the case of a system with onecapacitor. The noise improvement can be calculated as follows:

For a one pole roll-off with f_(P)=10 MHz, the integrated noise from 10MHz to 100 MHz is:

$\mspace{20mu}\begin{matrix}{\left. \left( {I_{O}/I_{n,{gm}}} \right)^{2} \right| = {{1/\left( {1 + {\omega^{2}{C^{2}/g_{m}^{2}}}} \right)}}} \\{= {{{1/\left( {1 + {\left( {2\pi} \right)^{2}f^{2}{C^{2}/g_{m}^{2}}}} \right)}} \approx {\left( {2\pi} \right)^{2}*{\left( {C/g_{m}} \right)^{2}/f^{2}}}}}\end{matrix}$ $\mspace{20mu}\begin{matrix}{{S_{5}^{2}(f)} = {\int_{10*f_{P}}^{f_{P}}{\left( {2\pi} \right)^{2}*\left( {C/g_{m}} \right)^{2}*{{df}/f^{2}}}}} \\{= {{\left( {1/3} \right)*\left( {{1/2}\pi} \right)*{\left( {g_{m}/C} \right)/f^{3}}}|_{f_{P}*10}^{f_{P}}}} \\{= {\left( {1/3} \right)*\left( {{1/2}\pi} \right)*\left( {g_{m}/C} \right)*\left( {1 - {1/\left( {10 - 1} \right)^{2}}} \right)}} \\{\approx {\left( {1/3} \right)*f_{P}}}\end{matrix}$ $\mspace{20mu}\begin{matrix}{{S_{6}^{2}(f)} = {{\int_{10*f_{P}}^{f_{P}}{\left( {2\pi} \right)^{2}*\left( {C/g_{m}} \right)^{2}*{{df}/f^{4}}}} = {\left( {1/5} \right)*\left( {{1/2}\pi} \right)*}}} \\{{\left( {g_{m}/C} \right)/f^{5}}|_{f_{P}*10}^{f_{P}}} \\{= {\left( {1/5} \right)*\left( {{1/2}\pi} \right)*\left( {g_{m}/C} \right)*\left( {1 - {1/\left( {10 - 1} \right)^{4}}} \right)}} \\{\approx {\left( {1/5} \right)*f_{P}}}\end{matrix}$S₅²(f)/S₆²(f) = (1/3) * f_(P)/(1/5) * f_(P) = 5/3 =  > 10 * log₁₀(5/3) = 2.2  dB.

In summary, the current-mode S/H circuit performance can be summarizedas follows:

1. The total thermal noise improvement is 5.4 dB, if we just drive andsense the circuit with current instead of voltage.

2. Much more performance gain is achieved when a true 1/f noisecharacteristic for the switches is considered. Because the current-modecircuit has a HP noise transfer, it cancels 1/f noise low frequencycomponent. If the HP starts at dc the noise improvement may reach 65 dBor more.

3. However, in practical circuits it is expected that the HP starts notat dc-, but at higher frequency, so that the low end is not compensated.However, some performance improvement due to 1/f noise cancellationalways exists. For a just a decade of HP noise transfer function,another 4.8 dB is gained. Then the total circuit noise improvement(thermal and 1/f) is close to 10.2 dB.

4. Finally, adding second capacitor—C₂ in the current-mode circuitresults in a faster roll-off. The noise improvements depend on thecircuit parameters, but for a typical case they are calculated to be 2.2dB. Hence, the total circuit noise improvement may reach 12.4 dB.

5. In some aspects the current-mode circuit may have as much as 10 dBlower noise as compared to a voltage-mode, which is well within thereach due to a 2 dB margin.

A current-mode S/H circuit has been presented. Modification of thecircuit may become apparent in those of ordinary skill in the art uponreading the present disclosure, and it is intended that the scope of theinvention disclosed herein be limited only by the broadestinterpretation of the appended claims to which the inventor is legallyentitled.

I claim:
 1. A sample-and-hold circuit with an enhanced noise limit, thesample-and-hold circuit comprising: a first field effect transistor(FET) having a first source drain (S/D) to accept an analog input signalcurrent (I_(S)), a second S/D, and a gate to accept a binary level firstdigital control signal; second FET having a second S/D connected to thefirst S/D of the first FET, a first S/D connected to the second S/D ofthe first FET, and a gate to accept a binary level second digitalcontrol signal, complementary to the first digital control signal; asource resistance (Rs) between the first S/D of the first FET andground; a first capacitor (C₁) having a first terminal connected to thefirst S/D of the first FET, and a second terminal connected to ground;and, wherein the second S/D of the first FET presents a current-sensedanalog output signal (I_(O)) in response to the first and second digitalcontrol signals respectively enabling the first and second FETs at afirst time.
 2. The sample-and-hold circuit of claim 1 wherein thecombination of the first FET, second FET, source resistance, and firstcapacitor create a lowpass current signal transfer function.
 3. Thesample-and-hold circuit of claim 2 wherein the lowpass current signaltransfer function is represented as follows:I _(O) /I _(S) =g _(m)/(g _(m) +sC ₁); where s is a complexfrequency=jω; where j is an imaginary unit; where ω=2 ·π·frequency;where C₁ represents the capacitance value of C₁; and, where g_(m) is thetransconductance of the first and second FETs.
 4. The sample-and-holdcircuit of claim 3 wherein the combination of the first FET, second FET,source resistance, and first capacitor create a highpass noise transferfunction.
 5. The sample-and-hold circuit of claim 4 wherein the highpassnoise transfer function is represented as follows:(I _(O) /I _(n,gm))=sg _(m) C ₁/(g _(m) +sC ₁); and, where I_(n,gm) is aswitch noise current source associated with the first and second FETs.6. The sample-and-hold circuit of claim 5 wherein a combined noisetransfer function, derived from the lowpass current transfer function(I_(O)/I_(S)) and highpass noise transfer function (I_(O)/I_(n,gm)) isrepresented as follows:(I _(O) /I _(n,gm))·(I _(O) /I _(S))=sg _(m) C ₁/(g _(m) +sC ₁)².
 7. Thesample-and-hold circuit of claim 6 wherein the combination of the firstFET, second FET, source resistance, and first capacitor create a flatspectrum flicker (1/f) noise response from the first and second FETcorner frequency (f_(P)) to a sampling frequency (f_(S)), when 1/R_(S)is at least an order of magnitude less than g_(m).
 8. Thesample-and-hold circuit of claim 6 wherein the combination of the firstFET, second FET, source resistance, and first capacitor create a flatthermal noise (I(f)_(noise)) response from the first and second FETcorner frequency (f_(P)) to a sampling frequency (f_(S)), when 1/R_(S)is at least an order of magnitude less than g_(m).
 9. Thesample-and-hold circuit of claim 8 whereinI ²(f)_(noise)=0.1427·kT·g _(m); where k is the Boltzmann constant; and,where T is the Kelvin temperature.
 10. The sample-and-hold circuit ofclaim 1 further comprising: a second capacitor (C₂) having a firstterminal connected to the second S/D of the first FET and a secondterminal connected to ground.
 11. The sample-and-hold circuit of claim10 further comprising: an output resistance (R_(O)) between the secondS/D of the first FET and ground; wherein the combination of the firstFET, second FET, source resistance, output resistance, first capacitor,and second capacitor create a lowpass current signal transfer functionrepresented as follows:I _(O) /I _(S)=(g _(m) /R _(O) C ₁ C ₂)/[s ² +sg _(m)(C ₁ +C ₂)/C ₁ C ₂+g _(m) /R _(S) C ₁ C ₂], where g _(m) ·R _(O) is at least greater than10; where s is a complex frequency=jω; where j is an imaginary unit;where ω=2 ·π·frequency; where C₁ represents the capacitance value of C₁;where C₂ represents the capacitance value of C₂; and, where g_(m) is thetransconductance of the first and second FETs.
 12. A sample-and-holdcircuit with an enhanced noise limit, the sample-and-hold circuitcomprising: at least a first field effect transistor (FET) having afirst source drain (S/D) to accept an analog input signal current(I_(S)), a second S/D, and a gate to accept a binary level first digitalcontrol signal; a source resistance (R_(S)) between the first S/D of thefirst FET and ground; a first capacitor (C₁) having a first terminalconnected to the first S/D of the first FET and a second terminalconnected to ground; a second capacitor having a first terminalconnected to the second S/D of the first FET and a second terminalconnected to ground; and, wherein the second S/D of the first FETpresents a current-sensed analog output signal (I_(O)) in response tothe first digital control signal enabling the first FET at a first time.13. The sample-and-hold circuit of claim 12 further comprising: anoutput resistance (R_(O)) between the second S/D of the first FET andground; wherein the combination of the first FET, source resistance,output resistance, first capacitor, and second capacitor create alowpass current signal transfer function represented as follows:I _(O) /I _(S)=(g _(m) /R _(O) C ₁ C ₂)/[s ² +sg _(m)(C ₁ +C ₂)/C ₁ C ₂+g _(m) /R _(S) C ₁ C ₂], when g _(m) ·R _(O) is at least greater than10; where s is a complex frequency=jω; where j is an imaginary unit;where ω=2 ·n ·frequency; where C₁ represents the capacitance value ofC₁; where C₂ represents the capacitance value of C₂; and, where g_(m) isthe transconductance of the first FET.